[Technical Field to which the Invention Belongs]
The present invention relates to a semiconductor device having a circuit comprising a thin film transistor (hereafter referred to as TFT), and to a method of manufacturing thereof. For example, the present invention relates to an electro-optical device, typically a liquid crystal display panel, and to electronic equipment loaded with this type of electro-optical device as a part.
Note that, throughout this specification, semiconductor device denotes a general device which can function by utilizing semiconductor characteristics and that the category of semiconductor devices includes electro-optical devices, semiconductor circuits, and electronic equipment.
In recent years, techniques of structuring a thin film transistor (TFT) by using a semiconductor thin film (with a thickness on the order of several nm to several hundred of nm) formed over a substrate having an insulating surface have been in the spotlight. The thin film transistor is being widely applied in an electronic device such as an IC or an electro-optical device, and in particular, its development as a switching element of an image display device has been proceeding rapidly.
Conventionally, a liquid crystal display device is known as an image display device. Active matrix liquid crystal display devices have come into widespread due to the fact that, compared to passive liquid crystal display devices, a higher precision image can be obtained. By driving pixel electrodes arranged in a matrix state in the active matrix liquid crystal display device, a display pattern is formed on a screen in an active matrix liquid crystal display device. In more detail, by applying a voltage between a selected pixel electrode and an opposing electrode corresponding to the pixel electrode, optical modulation of a liquid crystal layer arranged between the pixel electrode and the opposing electrode is performed, and the optical modulation is recognized as a display pattern by an observer.
The use of this type of active matrix liquid crystal display device is spreading, and along with making the screen size larger, demands for higher precision, higher aperture ratio, and higher reliability are increasing. Further, at the same time, demands are increasing for improving productivity and lowering costs.
Conventionally, an amorphous silicon film is ideally used as an amorphous semiconductor film because of the capability of forming it on a large surface area substrate at a low temperature equal to or less than 300xc2x0 C. Further, a reversed stagger type (or bottom gate type) TFT having a channel forming region formed by an amorphous semiconductor film is often used.
[Problem to be Solved by the Invention]
Conventionally, the production costs have been high in order to manufacture a TFT on a substrate with a technique of photolithography using at least 5 photomasks for an active matrix type liquid crystal display device. In order to improve productivity and yield, reducing the number of steps is considered as an effective means.
Specifically, it is necessary to reduce the number of photomasks needed to manufacture the TFT. The photomask is used in a photolithography technique in order to form a photoresist pattern, which becomes an etching process mask, over the substrate.
By using one photomask, there are applied with steps such as applying resist, pre-baking, exposure, development, and post-baking, and in addition, steps of film deposition and etching, resist peeling, cleaning, and drying are added before and after these steps. Therefore, the entire process becomes complex, which leads to a problem.
Further, static electricity is generated by causes such as friction during manufacturing steps because the substrate is an insulator. Short circuits develop at an intersection portion of wirings formed on the substrate when static electricity is generated, and then deterioration or breakage of the TFT due to static electricity leads to display faults or deterioration of image quality in liquid crystal display devices. In particular, static electricity develops during rubbing in the liquid crystal aligning process performed in the manufacturing steps, and this becomes a problem.
The present invention is for solving such problems, and an object of the present invention is to reduce the number of steps for manufacturing a TFT, and to realize a reduction in the production cost and an improvement in yield for a semiconductor device typified by an active matrix type liquid crystal display device.
Further, an object of the present invention is to provide a structure and a method of manufacturing the structure for resolving the problems of damage to the TFT and deterioration of TFT characteristics due to static electricity.
[Means for Solving the Problem]
In order to solve the above problems, in the present invention, first, a gate wiring line is formed by a first photomask.
Next, a gate insulating film, a non-doped amorphous silicon film (hereinafter referred to as a-Si film), an amorphous silicon film containing an impurity element to give an n-type conductivity (hereinafter referred to as n+a-Si film), and a conductive film are continuously formed.
Next, a gate insulating film, an active layer comprising the a-Si film, a source wiring line (including a source electrode), and a drain electrode are formed through patterning by a second photomask.
Thereafter, after a transparent conductive film is formed, a pixel electrode made of the transparent conductive film is formed by a third photomask, and further, at the same time that a source region and a drain region comprising the n+a-Si film are formed, a part of the a-Si film is removed.
By adopting such structure, the number of photomasks used in a photolithography technique can be made three.
Further, the source wiring is covered by a transparent conductive film comprising the same material as the pixel electrode, a structure which protects the entire substrate from eternal static electricity or the like is used. Furthermore, a structure in which a protecting circuit is formed using the transparent conductive film may also be used. The generation of static electricity due to friction between production equipment and the insulating substrate can be prevented during manufacturing processing by using this type of structure. In particular, the TFTs can be protected from static electricity generated during a liquid crystal alignment process of rubbing performed during manufacturing steps.
A structure of the present invention disclosed in this specification is:
a semiconductor device possessing a gate wiring, a source wiring, and a pixel electrode, having:
the gate wiring 102 formed on an insulating surface;
the insulating film 110 formed on the gate wiring;
the amorphous semiconductor film 122 formed on the insulating film;
the source region 123 and the drain region 124 formed on the amorphous semiconductor film;
the source wiring 125 or the electrode 126 formed on the source region or the drain region; and
the pixel electrode 127 formed on the electrode;
characterized in that:
one end surface of the drain region 124 or the source region 123 reversed corresponds with an end surface of the insulating film 110, an end of the amorphous semiconductor film 122 and an end surface of the electrode 126.
Further, another structure of the present invention is:
a semiconductor device possessing a gate wiring, a source wiring, and a pixel electrode, having:
the gate wiring 102 formed on an insulating surface;
the insulating film 110 formed on the gate wiring;
the amorphous semiconductor film 122 formed on the insulating film;
the source region 123 and the drain region 124 formed on the amorphous semiconductor film;
the source wiring 125 or the electrode 126 formed on the source region or the drain region; and
the pixel electrode 127 formed on the electrode;
characterized in that:
one end surface of the drain region 124 or the source region 123 reversed corresponds with an end surface of the insulating film 110, an end surface of the amorphous semiconductor film 122 and an end surface of the electrode 126; and
the other end surface of the drain region 124 or the source region 123 reversed corresponds with an end surface of the pixel electrode 127 and the other end surface of the electrode 126.
Further, each of the above structures is characterized in that the source region and the drain region comprises an amorphous semiconductor film containing an impurity element which imparts n-type conductivity.
Still further, each of the above structures is characterized in that the insulating film, the amorphous semiconductor film, the source region, and the drain region are formed in succession without exposure to the atmosphere.
In addition, each of the above structures is characterized in that the insulating film, the amorphous semiconductor film, the source region, or the drain region is formed by a sputtering method.
Additionally, each of the above structures is, as shown in FIG. 2(D), characterized in that the source region 123 and the drain region 124 are formed by using the same mask as that of the amorphous semiconductor film 122 and the electrode 126. Moreover, it is characterized in that the source region and the drain region are formed by using the same mask as that of the source wiring 125.
Further, each of the above structures is, as shown in FIG. 2(D), characterized in that the source region 123 and the drain region 124 are formed by using the same mask as that of the source wiring 125 and the pixel electrode 127.
In addition, in each of the above structures, by etching process shown in FIG. 2(D), there is provided a structure in which, in the amorphous semiconductor film, the film thickness in a region that contacts with the source region and the drain region is formed thicker than the film thickness in a region between a region that contacts with the source region and a region that contacts with the drain region, that is, a channel etch type bottom gate structure.
Besides, the structure of the invention for realizing the above construction is a method of fabricating a semiconductor device, characterized by comprising:
a first step of forming a gate wiring line 102 by using a first mask;
a second step of forming an insulating film 104 covering the gate wiring line;
a third step of forming a first amorphous semiconductor film 105 on the insulating film;
a fourth step of forming a second amorphous semiconductor film 106 containing an impurity element to give an n-type conductivity on the first amorphous semiconductor film;
a fifth step of forming a first conductive film 107 on the second amorphous semiconductor film;
a sixth step of forming a wiring line 116 (a source wiring line and an electrode) by selectively removing the insulating film 104, the first amorphous semiconductor film 105, the second amorphous semiconductor film 106, and the first conductive film 107 by using a second mask;
a seventh step of forming a second conductive film 118 being in contact with and overlapping with the wiring line 116 (the source wiring line and the electrode); and
an eighth step of forming a source region 123 and a drain region 124 comprising the second amorphous semiconductor film, and a pixel electrode 127 made of the second conductive film by selectively removing a part of the first amorphous semiconductor film 112, the second amorphous semiconductor film 114, the first conductive film 116, and the second conductive film 118 by using a third mask.
Besides, in the above structure, it is characterized in that formation is continuously made without being exposed to the air from the second step to the fifth step.
Besides, in the above respective structures, it is characterized in that formation is continuously made in the same chamber from the second step to the fifth step.
Besides, in the above respective structures, the insulating film may be formed by a sputtering method or a plasma CVD method.
Besides, in the above respective structures, the first amorphous semiconductor film may be formed by a sputtering method or a plasma CVD method.
Besides, in the above respective structures, the second amorphous semiconductor film may be formed by a sputtering method or a plasma CVD method.
Besides, in the above respective structures, it is characterized in that the second conductive film is a transparent conductive film or a conductive film having reflectivity.
[Embodiment Mode of the Invention]
The mode of carrying out the invention will be described below.
FIG. 1 is an example of a plan view of an active matrix substrate of the present invention, and here, for simplification, one pixel structure among a plurality of pixels arranged in matrix form is shown. FIGS. 2 and 3 are views showing a fabricating process.
As shown in FIG. 1, this active matrix substrate includes a plurality of gate wiring lines arranged in parallel with each other, and a plurality of source wiring lines perpendicular to the respective gate wiring lines.
A pixel electrode 127 comprising a transparent conductive film is disposed at a region surrounded by the gate wiring lines and the source wiring lines. Besides, a transparent conductive film 128 overlaps with the source wiring line so as not to overlap with the pixel electrode 127.
Further, a capacitance wiring line 103 is disposed below the pixel electrode 127, between adjacent two gate wiring lines, and in parallel with the gate wiring line 102. This capacitance wiring line 103 is provided for every pixel, and forms a storage capacitor with an insulating film 111 shown in FIG. 2(B) as a dielectric.
Besides, a TFT as a switching element is provided in the vicinity of an intersection of the gate wiring line 102 and the source wiring line 125. This TFT is a reversed stagger type (or bottom gate type) TFT including a channel formation region comprising a semiconductor film having an amorphous structure (hereinafter referred to as an amorphous semiconductor film).
Besides, in this TFT, a gate electrode (formed integrally with the gate wiring line 102), a gate insulating film, an a-Si film, a source region and a drain region comprising an n+a-Si film, a source electrode (formed integrally with the source wiring line 125), and an electrode 126 (hereinafter also referred to as a drain electrode) are sequentially formed to be laminated on an insulating substrate.
Besides, the gate insulating film does not exist over the gate wiring line in a region where the gate wiring line does not overlap with the a-Si film.
Thus, the pixel electrode 127 overlapping with the electrode 126 is formed so as not to overlap with the gate wiring line.
Besides, at the intersection of the gate wiring line and the source wiring line, the transparent conductive film at the end portion of the source wiring line is removed so as to prevent shorting. Besides, the end of an electrode 117 is removed so as to prevent shorting between the capacitance wiring line and the pixel electrode.
Besides, under the source wiring line (including the source electrode) and the drain electrode 126, the gate insulating film, the a-Si film, and the n+a-Si film are sequentially formed to be laminated on the insulating substrate.
Besides, the a-Si film in a region between a region that contacts with the source region and a region that contacts with the drain region, is thin as compared with that in the other regions. The film is thin since, when the n+a-Si film was separated by etching to form the source region and the drain region, a part of the a-Si film was removed. Besides, by this etching, an end surface of the pixel electrode, an end surface of the drain electrode, and an end surface of the drain region are coincident with each other.
Besides, similarly, an end surface of the transparent conductive film covering the source electrode, an end surface of the source region, and an end surface of the source wiring line are coincident with each other.